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NXP Semiconductors /LPC43xx /USB0 /USBINTR_D

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Interpret as USBINTR_D

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (UE)UE 0 (UEE)UEE 0 (PCE)PCE 0 (RESERVED)RESERVED 0 (RESERVED)RESERVED 0 (RESERVED)RESERVED 0 (URE)URE 0 (SRE)SRE 0 (SLE)SLE 0 (RESERVED)RESERVED0 (NAKE)NAKE 0 (RESERVED)RESERVED 0 (RESERVED)RESERVED 0 (RESERVED)RESERVED 0 (RESERVED)RESERVED

Description

USB interrupt enable (device mode)

Fields

UE

USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS.
UEE

USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register.
PCE

Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS.
RESERVED

Not used by the Device controller.
RESERVED

Reserved
RESERVED

Not used by the Device controller.
URE

USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit.
SRE

SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit.
SLE

Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit.
RESERVED

Reserved
NAKE

NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated.
RESERVED

Reserved
RESERVED

Not used by the Device controller.
RESERVED

Not used by the Device controller.
RESERVED

Reserved

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data